A novel fixed-point leaky sign regressor algorithm based adaptive noise canceller for PLI cancellation in ECG signals

In this paper, a novel fixed-point Leaky Sign Regressor Algorithm (LSRA) based adaptive noise canceller has been employed for the cancellation of 60 Hz Power Line Interference (PLI) from the ElectroCardioGram (ECG) signal. A sufficient condition for the convergence in the mean of the LSRA algorithm is also derived. The fixed-point LSRA-based adaptive noise canceller employed in this work is fully quantized using an in-house quantize function. The most effective number of quantization bits required for the various parameters are found to be 6-bits and are determined through rigorous simulations. The filtered ECG signal free from 60 Hz PLI is successfully recovered using a novel 6-bit fixed-point LSRA-based adaptive noise canceller

A New Fixed Point Noise Cancellation Method for Suppressing Power Line Interference in Electrocardiogram Signals

In this article, a new fixed point Leaky Sign Regressor Least Mean Mixed Norm (LSRLMMN) powered adaptive noise cancellation technique is being used for eliminating the Power Line Interference (PLI) noise embedded in the ElectroCardioGram (ECG) signal. The fixed point LSRLMMN powered noise cancellation technique used in this article has been completely quantized. The intention for the extensive quantization study and modeling approach was with a view to the physical integrated circuit implementation. All the modeling and simulation studies were carried out at the bit-level with various loss of precision schemes to ensure compliance with the set specification. The filter coefficients and all the data paths are quantized in order to establish at a high-level behavioral level of the parameters for a decreased complexity in integrated circuit implementation

Nonlinear-Stability Analysis of Higher Order Δ–Σ Modulators for DC and Sinusoidal Inputs

Abstract—The present work that exists on predicting the stability of Δ–Σ modulators is confined to DC input signals and unity quantizer gains. This poses a limitation for numerous Δ–Σ modulator applications. The proposed research work gives the stability curves for DC, sine, and dual sinusoidal inputs for any value of the quantizer gain. The maximum stable input limits for third-, fourth-, and fifth-order Chebyshev-Type-II-based Δ–Σ modulators are established using the describing-function method for DC and sinusoidal inputs. Closed-form mathematical expressions for the gains of the quantizer for higher order Δ–Σ modulators whose inputs are two concurrent sinusoids are derived from first principles. The derived stability curves are shown to agree reasonably well with the simulation results for different types of input signals and amplitudes

System and circuit level design and analysis of a 16-bit sigma-delta ADC for a TETRA-2 network mobile station application

This paper outlines a comprehensive design evaluation for development of a 16-bit Sigma-Delta (Σ-Δ) Analog-to-Digital Converter (ADC) for TETRA-2 Network Mobile Station (MS). A step-by-step design approach is described commencing from system-level evaluation leading to the circuit design, which would serve as a useful reference to designers involved with development of ADCs for wireless equipment

Stability Analysis of Higher-Order Delta-Sigma Modulators for Dual Sinusoidal Inputs

The aim of this paper is to determine the stability of higher-order Δ-Σ modulators for sinusoidal inputs. The nonlinear gains for the single bit quantizer for a dual sinusoidal input have been derived and the maximum stable input limits for a fifth-order Chebyshev Type II based Δ-Σ modulators are established. These results are useful for optimising the design of higher-order Δ-Σ modulators

Accurate stability prediction of single-bit higher-order Δ-Σ modulators for Speech Codecs

Present approaches for predict of Delta-Sigma (Δ-Σ) modulators are mo DC inputs. This poses limitations as pract of Δ-Σ modulators involve a wide range than DC such as speech, audio and multip the case for synthetically generated spee any other signal, through the appropriat multiple sinusoids. In this paper, a quasi linear model that accurately predicts stability of single-loop 1-bit higher order (Δ-Σ) modulators for mulitple sinusoids is given. The results of this paper would enable optimization of the design of higher-order single-loop (Δ-Σ) modulators with increased dynamic ranges for various applications that deploy multiple sinusoidal inputs, as well as any general input signal constructed from multiple sinusoids

A Study on the Effects of Accumulated and Independent Clock Jitter on Discrete-Time Delta- Sigma Modulators

This paper describes the effects of accumulated and independent clock jitters on the tonality and the Signal-to-Noise Ratio (SNR) of discrete-time Δ-Σ modulators. Simulations demonstrate that accumulated clock jitter exhibits increased tonality in the magnitude spectrum of the Δ-Σ modulator output especially at very high frequencies, while having no significant effect on the SNR. Independent clock jitter, on the other hand, degrades SNR performance but causes no increase in tonality

Nonlinear Model-Based Approach for Accurate Stability Prediction of One-Bit Higher-Order Delta-Sigma (Δ-Σ)Modulators

The present approaches on predicting stability of Delta-Sigma (Δ-Σ) modulators are mostly confined to DC inputs. This poses limitations as practical applications of Δ-Σ modulators involve a wide range of signals other than DC. In this paper, a quasi-linear model for Δ-Σ modulators with nonlinear feedback control analysis is presented that accurately predicts the stability of higher-order single-loop 1-bit Δ-Σ modulators for various types of input signals such as single-sinusoids, dual-sinusoids, multiple-sinusoids and Gaussian. Theoretical values are shown to match closely with simulation results. The results of this paper would significantly speed up the design and evaluation of higher-order single-loop 1-bit Δ-Σ modulators for various applications including those that may require multiple-sinusoidal inputs or any general input composed of a finite number of sinusoidal components, circumventing the need to perform detailed time-consuming simulations to quantify stability limits. By using the proposed method, the difference between the predicted and the actual stable amplitude limits results in an error of less than 1 dB in the in-band Signal-to-Noise Ratio (SNR) for 3rd- and higher-order Δ-Σ modulators for single-sinusoidal inputs. For single-, dual-, multiple-sinusoidal and Gaussian inputs the error is less than 2 dB for the 5th-order and reduces to less than 1 dB for 6th- and higher-order Δ-Σ modulators

Nonlinear Stability Prediction of Multibit Delta-Sigma Modulators for Sinusoidal Inputs

This paper proposes a novel algorithm that can be integrated with various design and evaluation tools, to more accurately and rapidly predict stability in multi-bit delta-sigma (Δ-Σ) modulators. Analytical expressions using the nonlinear gains from the concept of modified nonlinearity in control theory are incorporated into the mathematical model of multi-bit Δ-Σ modulators to predict the stable amplitude limits for sinusoidal input signals. The nonlinear gains lead to a set of equations which can numerically estimate the quantizer gain as a function of the input sinusoidal signal amplitude. This method is shown to accurately predict the stable amplitude limits of sinusoids for 2nd-, 3rd-, 4th-, 5th- and 6th-order 3- and 5-level mid-tread quantizer based Δ-Σ modulators. The algorithm is simple to apply and can be extended to midrise quantizers or to any number of quantizer levels. The only required input parameters for this algorithm are the number of quantizer levels and the coefficients of the noise transfer function